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LEON3 SoftCore

Implementation of Softcore LEON3 on a Microsemi FPGA based constrained HW platform, using a fine tuning of the processor profile and replacing HW ipcores by SW implementations. The system uses Emtech propietary SW to debug and upload firmware to the board.  

3PA1 Board + Daughter Card:

• FPGA ProASIC3 A3P600

• 48 External GPIO

• 40MHz clock on board

• 1MByte of RAM (Daughter Card)

• 16MBytes FLASH (Daughter Card)


• Leon3 Softcore 

• FreeRTOS

Programming Languages Used

• FreeRTOS.

• Embedded C.

• Low lever assembly language design.

• Microsemi ProAsic3 FPGA

• FPGA design using Libero SoC.

• Leon3 Softcore CPU 

Upper view
Lower view

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