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Emtech SDK

IDE based on Eclipse as a development environment for microcontrollers ARM embedded.


Lanín CM4 Board

This board is intended for development of custom applications based on Cortex M4 microcontroller STM32F417ZGT6. It has the resources needed for rapid development. Through a single USB connection is possible to power the board, configure and debug the firmware via JTAG interface. 

Also, we implemented an IDE based on Eclipse, with tutorials and examples that permits you start from scratch a new application development on this platform.


FTHL Board

We design this board in order to have a tool when we need to program devices via JTAG, such as FPGAs, microcontrollers, etc. 

With this design we have a USB 2.0 JTAG interface implemented with the chip manufacturer FTDI FT2232HL. Also this board has a RS-232 serial communication interface and 3.3V levels available, which gives us a number of possible applications.


DTR3 Board

The DRT3 multipurpose board, was designed to implement a graphical interface touch screen with 2.4'' TFT LCD. Furthermore, two buttons and two additional LEDs for general use is added.


DTR2 Board

The DTR2 board was designed to give the user a visual interface more flexible than its predecessor, it has a 16-character alphanumeric display, 2 lines; also include 8 BUTTONS, a DIPSWITCH of 4 position indicators and 8 LEDs.


Chalten XA-1 Board


It is a board designed to perform tasks that require high processing power, high speed data transfer and numerous input-output (I / O). "Daughters" boards can be adapted expanding its capacity and add the desired components and new interfaces. 

The board incorporates an ARM9 processor with the capability to run Linux and a Xilinx FPGA Spartan3. Along with the board we offer a cores and software required to provided communication between the FPGA and microprocessor, avoiding the need of Linux kernel modifications. The core of the FPGA has an AMBA bus to facilitate the integration of new custom made cores.


3PA1 Board

The 3PA1 is a flexible board, created for projects that require high processing power, high speed data transfer. The board has several input-output (I/O) to plug "Daughters" that can be added to the board in order to expand the initial capacity by adding the desired components. 

The board permits the use of VQ100 or PQ208 encapsulated, whereby different versions of Actel FPGA can be welded on the board, among which are A3P030, A3P060, A3P125, A3P250, A3P400, A3P600 and A3P1000.


3PX1 Board

The 3PX1 board was designed for teaching, based on FPGA Xilinx Spartan 6. Includes all necessary resources to begin developing and testing digital designs (cores) without the need for programmers or additional instruments. This makes it ideal for learning hardware description languages ​​(HDL) and digital techniques in order to get a rapid prototyping of digital systems.


DTR1 Board

This board was designed to give to the user the opportunity to have a quick and complete overview of the design, using standard components in an electronic system such as LEDs, DIP switches, 7-SEGMENT DISPLAYS, PUSHBUTTON and BUFFERS. The connectors and measurements of the board to gives us the ability to directly connect the DTR1 to the CHALTÉN and 3PA1 boards designed by the company, without the need of any wiring.


ADC/DAC Mezzanine Card

The FMC01 Mezzanine card was designed to digitize and synthetize high speed signals. Its two ADC channels and two DAC channels allow the user to acquire or generate high–speed signals, i.e. for radar test systems. The board has been characterized and we have developed a HW/SW application framework based on the ZedBoard (Xilinx Zynq FPGA) to test and evaluate every component on the card.  


LEON3 SoftCore

Implementation of Softcore LEON3 on a Microsemi FPGA based constrained HW platform, using a fine tuning of the processor profile and replacing HW ipcores by SW implementations. The system uses Emtech propietary SW to debug and upload firmware to the board.  


Advanced Verification Enviroment Development for SoC

This project consisted in the Verification of the System On Chip (SoC) designed to be the main controller of a Critical System and implemented into a multimillion gate FPGA. The SoC incorporates a general purpose processor, several application specific cores and controllers; all connected with a multi-master AXI bus and fault detection & recovery resources. It also handles several dedicated interfaces with stringent timing constraints, as well as standard IO for DRAM, SRAM, Ethernet, USB and I2C interfaces.

Emtech lead the overall verification process, from test plan definition, to testbench implementation, DUV simulation and bug tracking. The verification environment was developed in System Verilog as a new instance of our continuously improved framework. The UVM base library was employed for the testbench architecture and in-house developed verification IPs (Agents) where integrated and reused. SV classes were extensively used to manage a complex Loosely Timed reference model that involves an instruction level simulator for the CPU and allows emulating all the high level transactions derived from ambitious functional coverage requirements.



This application includes the use of a Zynq-based processing board and ADC+DAC mezzanine card. The work consisted in the development of a hardware and software framework for signal acquisition, generation, processing and monitoring. The signals from the converters were processed in real-time at 200 Msps using the Zynq PL (FPGA), and analyzed offline using software on the Zynq PS (SoC). 

The PL (FPGA) design includes cores for clock management, DDR DAC and ADC interfaces, control blocks, and real-time filer implementations. The logic is mapped to the PS using an AXI-bridge block.

The PS (SoC) base software can perform FFTs on acquired data to analyze the input data channels. Linux is used as the SoC Operating System and an embedded web server implements the UI, including graphics based screens for management and monitoring of the PL functionality. This includes options to select signal source, control the ADC and DAC channels, define the filter coefficients and view signal characteristics (waveforms and frequency characteristics).